The present invention relates to a semiconductor integrated circuit device of a semiconductor device particularly including a logic integrated circuit or logic LSI or the like, a method of manufacturing the same and a method of manufacturing a mask formed with a pattern used therefor.
High performance/sophisticated features of a semiconductor integrated circuit are achieved by miniaturized formation/highly integrated formation of a circuit pattern. For example, in the case of logic LSI, speeding-up has been promoted by reducing a gate length of a transistor and sophisticated features has been achieved by increasing a circuit density per unit area. In accordance therewith, a pitch of arranging wirings (interconnected) for connecting logic gates to each other has rapidly been miniaturized. With regard to progress in the wiring pitch, although currently, a pitch of 0.8 through 0.4 xcexcm is considered to be achieved by using a KrF excimer laser exposure apparatus, further, a pitch of about 0.3 xcexcm is considered to be achieved by using an ArF excimer laser exposure apparatus, it is anticipated that a pitch smaller than 0.3 xcexcm is difficult to realize by a conventional reduction projection exposure method using deep ultra violet light. Hence, as a method of realizing a further smaller pattern, an electron beam writing method (or EB lithography), an X-ray exposure method (or proximity X-ray lithography) or the like has been investigated. Meanwhile, as a method of promoting resolution performance of an optical system without changing the optical system, there is known a phase-shifting mask. According to the method, phase of light transmitting through a specific light transmitting portion (also referred to as opening portion) on a mask is controlled (normally, reversed by 180 degrees), by which resolution of an optical system is significantly promoted in comparison with a case of using a conventional mask.
According to the phase shifting method, there is needed phase arrangement for determining at which portion of a circuit pattern the phase is reversed at a design stage. However, according to an actual circuit pattern, some patterns in which phase arrangement is essentially difficult may be produced. For example, a case in which U-shape patterns or three light transmitting patterns (that is, opening patterns) are arranged at distances the most proximate to each other, corresponds thereto and this is referred to as phase conflict. Since the problem is difficult to resolve, the phase-shifting mask has been applied and used to restrict to a simple pattern of a memory cell of the memory LSI or the like.
A method of avoiding the phase conflict even in the case of applying the phase-shifting mask to a complicated pattern has been reported by Oi et al. According thereto, a layout avoiding the phase conflict is calculated by carrying out compaction after phase arrangement at a symbolic level.
Other method of resolving the phase conflict is based on a concept of carrying out multiple exposure of a plurality of masks including the phase-shifting mask on the same photoresist layer. The concept has been patented by the inventors in Japanese Patent No. 2650962 and No. 2638561. Further, application of the concept to various circuit patterns has been reported. For example, an application for forming a gate pattern of a logic LSI has been filed for patent by Jinbo or Komatsu et al. (Japanese Patent Laid-Open No. Hei 5(1993)-204131, Japanese Patent Laid-Open No. Hei 6(1994)-67403). Further, a method of applying the concept to a wiring has been filed by B. J. Lin et al. (Japanese Patent Laid-Open No. Hei 8 (1996)-227140). Further, an arbitrary pattern generation algorithm by a phase-shifting mask using a phase retrieval method has been proposed by Y. C. Pati et al. (SPIE: Optical/Laser Microlithography VII, SPIE Vol. 2197 (1994) pp.314-327).
However, the above-described electron beam writing method or X-ray exposure method poses the following problems. First, according to the electron beam writing method, enormous time is taken for successively writing individual patterns. Hence, there is investigated a cell projection method capable of transcribing all pattern of a certain degree of a scale (for example, about 5 xcexcm square), however, a kind of a pattern which can be set is limited and therefore, the method is not effective in a random wiring pattern of a logic LSI. Further, although there has been investigated an SCALPEL method capable of carrying out scanning exposure of a large area mask, the throughput is greatly reduced compared with that of the current exposure method.
Further, according to the X-ray exposure method, there poses a problem that it is difficult to realize a mask having sufficient accuracy.
Meanwhile, there poses the following problems in various methods which have been proposed conventionally for applying the phase-shifting mask method to an actual complicated circuit pattern.
For example, according to the method of carrying out compaction after phase arrangement at a symbolic level, a circuit dimension of the portion of producing the phase conflict is alleviated and therefore, the method is essentially counter to miniaturization of circuit.
Meanwhile, a logic LSI in recent times exceeds a manually designable scale and almost all of logic LSI""s are designed by using an automatic place and route method. Therefore, it is necessary to generate a phase-shifting mask with respect to automatically generated enormous pattern data and it is nonrealistic to generate the phase-shifting mask manually by trial and error.
However, in the method of dealing with a complicated pattern by using multiple exposure of a plurality of masks, for example, according to Japanese Patent Laid-Open No. Hei 5(1993)-204131 or Japanese Paten Laid-Open No. Hei 8 (1996)-227140, a rule for decomposing an original design pattern into a plurality of masks is not generalized and therefore, there poses a problem that it is difficult to deal with actual enormous LSI data.
Further, methods disclosed in Japanese Patent Laid-Open No. Hei 5(1993)-204131 or Japanese Patent Laid-Open No. Hei 6(1994)-67403, are for miniaturizing a gate of a transistor and there poses a problem that it is difficult to reduce a wiring pitch by applying the methods to a wiring pattern.
Meanwhile, according to the method of decomposing a pattern in vertical and horizontal directions disclosed in Japanese Paten Laid-Open No. Hei 8(1996)-227140, it is difficult to correspond to an arbitrary pattern in a random wiring of a logic LSI. For example, when a circuit pattern 5 shown in FIG. 29 is decomposed in vertical and horizontal directions, two sheets of masks V and H are formed as shown by FIGS. 30(a) and 30(b), however, in this case, for example, phase conflict between two light transmitting portions (opening portions) X1 and X2 in the mask H is not resolved. In FIG. 30, numeral 1 designates a light blocking portion and numerals 2, 3 and 4 designate light transmitting portions (opening portions). According to the above-described publicly-known example, there is suggested a way of thinking that the light transmitting (opening) patterns X1 and X2 on the mask are further distributed to two sheets of masks, however, in this case, X1 and X2 constitute incoherent summation and therefore, it is difficult to clearly separate these. Further, since there is not given a general guiding principle therefor, it is difficult to apply the way to a large scale LSI pattern including an enormous random patterns for which manual operation is substantially impossible as described above.
Further, since a phase arranging method using the phase retrieval method requires an enormous amount of calculation and therefore, it is difficult to carry out the processing on the large scale data in a practical time period, further, the generated mask pattern is complicated, there poses a problem that a limit or the like in actually manufacturing a mask is not necessarily taken into consideration.
Meanwhile, the inventors have presented a method of capable of applying phase shift to an arbitrary pattern by a further general algorism in Digest of Technical Papers, 1999 Symposium on VLSI Technology (1999) pp.123-124, xe2x80x9cNode connection/quantum maskxe2x80x94Path to below 0.3-xcexcm pitch, proximity effect free random interconnect and memory patterningxe2x80x9d.
According to the method described in the 1999 Symposium on VLSI Technology, three sheets or more of masks are required for forming a wiring pattern and there poses a problem that the mask cost is increased.
As described above, there has not been a general and low cost method for making an alternating type phase shifting method applicable to a random wiring pattern. Therefore, there pose problems, (1) miniaturized formation of a circuit pattern of a logic LSI and a reduction in a chip area are determined by a limit of a wiring pitch of optical lithography using a conventional mask, and (2) the electron beam writing method having an extremely low throughput is obliged to use when a reduction in the wiring pitch exceeding a limit of optical lithography using the conventional mask is intended to achieve.
It is an object of the invention to provide an improved method of manufacturing a semiconductor integrated circuit device capable of forming a very small circuit pattern by a combination of a projection exposure method and a phase-shifting mask.
Thereby, a logic LSI such as a microcomputer which is random (irregular) and having an enormous amount of very small circuit patterns at low cost and in a short period of time. That is, by manufacturing a logic LSI having a random wiring pattern constituted by a very small wiring pattern having a wiring interval equal to or smaller than 0.15 xcexcm by using optical lithography, which has been regarded to be difficult realistically by the conventional optical lithography, high performance formation and high function formation of a semiconductor integrated circuit device can be achieved at low cost.
It is other object of the invention to provide a method of designing and manufacturing a mask pattern in which an alternating phase shifting is applicable to an arbitrary pattern by multiple exposure of at most two sheets of phase-shifting masks even in the case of a very small circuit pattern having random (irregular) and an enormous amount of wiring patterns or the like of a logic LSI, at low cost and in a short period of time.
A simple explanation will be given as follows of an outline of a representative aspect of the invention disclosed in the application.
The invention is carried out by analyzing characteristics of phase conflicts caused by shapes, arrangements and the like of various patterns in forming phase-shifting masks for a very small circuit pattern.
That is, the invention is carried out by analyzing various circuit patterns of logic LSI which has been regarded to be difficult to use conventional phase-shifting masks, analyzing characteristics of phase conflicts of particularly proximate patterns having straight lines, ends, L-shape portions and T-shape portions (that is, straight line portions running in parallel in vertical and horizontal directions, line-ends, corners and intersections or crossings) and rather utilizing the characteristics.
For example, according to a method of manufacturing a semiconductor integrated circuit device of the invention, in forming an opening pattern having a plurality of straight lines, ends and L-shape portions or T-shape portions in a photoresist film provided at an upper portion of a semiconductor region, the opening pattern is formed by subjecting the photoresist film to multiple projection exposure by using two sheets of masks comprising a first mask having a first light transmitting portion corresponding to the ends and the L-shape portions or T-shape portions of the pattern and a second mask having a second light transmitting portion corresponding to the straight lines.
Further, when the plural straight lines, ends and L-shape portions or T-shape portions of the opening pattern are arranged neighbouringly to other straight lines or ends at intervals equal to or smaller than 0.15 xcexcm, the first mask and the second mask are constituted by phase-shifting masks.
Further, according to other method of manufacturing a semiconductor integrated circuit device of the invention, in forming a circuit pattern running in vertical and horizontal directions in a photosensitive material provided at an upper portion of a semiconductor region, the circuit pattern is formed by subjecting the photosensitive material to multiple exposure by using a projection optical system by using a first phase shifting mask having a light transmitting portion corresponding to both of patterns running in parallel proximately to each other in a vertical direction of the circuit pattern and patterns running in parallel proximately to each other in a horizontal direction and a second phase-shifting mask having a light transmitting portion corresponding to any of line-ends, corners or intersections of the circuit pattern.
According to still other method of manufacturing a semiconductor integrated circuit device of the invention, in forming a pattern on a photosensitive substrate by subjecting the substrate to projection exposure by using a mask having a circuit pattern, the photosensitive substrate is subjected to multiple projection exposure by using a first phase-shifting mask including a first phase conflict resolving mask pattern for forming a mask light transmitting portion corresponding to a pattern region for constituting a first possible phase conflict region at a vicinity of a distal end portion of a line pattern having an adjacent pattern within a predetermined distance therefrom and a second phase conflict resolving mask pattern for forming a mask light transmitting portion corresponding to a pattern region for constituting a second possible phase conflict region at a vicinity of an intersection of a line pattern extended in a vertical direction and a line pattern extended in a horizontal direction, and a second phases shifting mask including a complimentary pattern for forming the predetermined circuit pattern by subjecting the photosensitive substrate to multiple exposure along with the first and the second phase conflict resolving mask patterns to thereby form a very small circuit pattern on the photosensitive substrate.
Further specifically, by subjecting a photoresist film to multiple projection exposure by the above-described masks by using KrF excimer laser, logic LSI constituted by a very small pattern having an irregular pitch equal to or smaller than 0.3 xcexcm (that is, pattern width is equal to or smaller than 0.15 xcexcm and pattern interval is equal to or smaller than 0.15 xcexcm) which has been regarded to be difficult to manufacture, can be manufactured with excellent reproducibility by using the conventional projection exposure technology. Further, similarly, when ArF excimer laser or F2 laser is used as a light source, a very small pattern respectively having a pitch of 0.23 xcexcm or a pitch equal to or smaller than 0.19 xcexcm can be dealt with.
Further, according to the invention, the circuit pattern is a pattern of a region corresponding to a light transmitting portion (referred to also as opening portion) on a mask, that is, an opening portion provided at, for example, a positive-tone photoresist film and actually signifies a pattern of any of a conductor region, a semiconductor region, or a nonconductive region other than the above-described region in planar arrangement of wirings or the like in a semiconductor device. Which of a conductor region, a semiconductor region or a nonconductive region is specified by a light transmitting region (that is, opening region, region for irradiating light to a photoresist film) of a mask, differs by whether a positive-tone resist is used or a negative tone resist is used in a pattern transcribing process, or whether a wiring pattern is formed by etching a wiring material in a wiring process, or a wiring material is embedded in a trench pattern in an insulator film by using what is called damascene process.
Furthermore, the two sheets of masks suitable for the invention are manufactured by the following procedure. That is, (1) when the light transmitting patterns arranged in parallel are proximate to each other such that a distance therebetween is within a predetermined value, phases of the light transmitting patterns are set such that phases of light projected between the two light transmitting patterns are reverse to each other, (2) in a plurality of the light transmitting patterns designated with phases thereby, when the light transmitting patterns having a same phase to be separated from each other are proximate to each other within the predetermined distance, proximate portions thereof and patterns at vicinities thereof are extracted and stored as first phase conflict region information in the meantime, when patterns to be consecutive are constituted by a plurality of the light transmitting patterns having different phases, overlap portions or contact portions of the plurality of light transmitting patterns having the different phases and patterns at vicinities thereof are extracted and stored as second phase conflict region information, (3) phase conflict resolving patterns for resolving phase conflicts are generated corresponding to corresponding respective regions by using the first and the second conflict region information, (4) complimentary patterns for forming the desired circuit pattern by subjecting a single photosensitive substrate to multiple exposure along with the phase conflict resolving patterns, are generated, (5) a first phase-shifting mask including the phase conflict resolving patterns and a second phase-shifting mask including the complimentary patterns are manufactured.